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S-7600A TCP/IP NETWORK PROTOCOL STACK LSI
Revision 1.2
Hardware Specification S-7600A
TCP/IP Network Protocol LSI
Seiko Instruments USA Inc. Phone +1-909-934-9334 Fax +1-909-975-5699 2990 West Lomita Boulevard Torrance, California 90505
Seiko Instruments Inc.
S-7600A
Hardware Specification
TABLE OF CONTENTS
1. INTRODUCTION .............................................................................................................................................. 1 1.1. PRODUCT OVERVIEW .................................................................................................................................. 1 1.2. FEATURES.................................................................................................................................................... 1 1.3. BENEFITS ............................................................................................................................... ...................... 1 1.4. TRADEMARKS............................................................................................................................................... 2 1.5. DEFINITIONS ............................................................................................................................... ................. 2 1.6. APPLICABLE DOCUMENTS ........................................................................................................................... 2 1.7. CAUTIONS .................................................................................................................................................... 2 2. FUNCTIONAL BLOCK DIAGRAM................................................................................................................ 3 3. TERMINALS ..................................................................................................................................................... 4 3.1. PIN ASSIGNMENT......................................................................................................................................... 4 3.2. PACKAGE DIMENSIONS................................................................................................................................ 5 3.3. PIN DESCRIPTION ........................................................................................................................................ 6 3.4. PIN CONFIGURATION ................................................................................................................................... 7 4. ELECTRICAL CHARACTERISTICS............................................................................................................. 8 4.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 8 4.2. RECOMMENDED OPERATING CONDITIONS ................................................................................................. 8 4.3. DC CHARACTERISTICS................................................................................................................................ 9 4.4. POWER CURRENT CONSUMPTION .............................................................................................................. 9 5. MPU INTERFACE .......................................................................................................................................... 10 5.1. OVERVIEW ................................................................................................................................................. 10 5.2. PARALLEL INTERFACE ............................................................................................................................... 10 5.2.1. 68k Family MPU Mode .................................................................................................................... 11
5.2.1.1. Write Cycle Timing ..................................................................................................................................... 11 5.2.1.2. Read Cycle Timing ............................................................................................................................... ...... 12
5.2.2. x80 Family MPU Mode .................................................................................................................... 13
5.2.2.1. Write Cycle Timing ..................................................................................................................................... 13 5.2.2.2. Read Cycle Timing ............................................................................................................................... ...... 14
5.3. SERIAL INTERFACE .................................................................................................................................... 15 5.3.1. Write Cycle Timing........................................................................................................................... 15 5.3.2. Read Cycle Timing........................................................................................................................... 16 5.4. INTERRUPT................................................................................................................................................. 17 6. MEMORY REQUIREMENTS ....................................................................................................................... 18 6.1. OVERVIEW ................................................................................................................................................. 18 6.2. MEMORY INTERFACE ARCHITECTURE....................................................................................................... 18 6.3. MEMORY MAP............................................................................................................................................ 19 7. S-7600A REGISTER DEFINITIONS ........................................................................................................... 20 7.1. OVERVIEW ................................................................................................................................................. 20 7.2. IAPI REGISTER MAP ................................................................................................................................. 20 7.3. REGISTER DEFINITIONS............................................................................................................................. 23 7.3.1. Revision Register (0x00)................................................................................................................ 23 7.3.2. General Control Register (0x01)................................................................................................... 23 7.3.3. Generic Socket Location Register (0x02).................................................................................... 24 7.3.4. Master Interrupt (0x04)................................................................................................................... 24 7.3.5. Serial Port Configuration / Status Register (0x08) ..................................................................... 25 7.3.6. Serial Port Interrupt Register (0x09) ............................................................................................ 27 i
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S-7600A
Hardware Specification
7.3.7. Serial Port Interrupt Mask Register (0x0A) ................................................................................. 27 7.3.8. Serial Port Data Register (0x0B) .................................................................................................. 28 7.3.9. BAUD Rate Divider Registers (0x0C-0x0D)................................................................................ 28 7.3.10. Our IP Address Registers (0x10-0x13)...................................................................................... 28 7.3.11. Clock Divider Registers (0x1C-0x1D) ........................................................................................ 29 7.3.12. Index Register (0x20)................................................................................................................... 29 7.3.13. Type of Service Register (TOS) (0x21) ..................................................................................... 29 7.3.14. Socket Config Status Low Register (0x22) ............................................................................... 30 7.3.15. Socket Status Mid Register (0x23)............................................................................................. 32 7.3.16. Socket Activate Register (0x24) ................................................................................................. 33 7.3.17. Socket Interrupt Register (0x26)................................................................................................. 33 7.3.18. Socket Data Available Register (0x28) ...................................................................................... 34 7.3.19. Socket Interrupt Mask Low Register (0x2A) ............................................................................. 35 7.3.20. Socket Interrupt Mask High Register (0x2B) ............................................................................ 35 7.3.21. Socket Interrupt Low Register (0x2C)........................................................................................ 36 7.3.22. Socket Interrupt High Register (0x2D)....................................................................................... 36 7.3.23. Socket Data Register (0x2E) ...................................................................................................... 37 7.3.24. TCP Data Send and Buffer Out Length Registers (0x30 - 0x31)........................................... 37 7.3.25. Buffer In Length Registers (0x32-0x33) .................................................................................... 37 7.3.26. Urgent Pointer / UDP Datagram Size Registers (0x34-0x35) ................................................ 37 7.3.27. Their Port Registers (0x36-0x37) ............................................................................................... 38 7.3.28. Our Port Registers (0x38-0x39).................................................................................................. 38 7.3.29. Socket Status High Register (0x3A) .......................................................................................... 38 7.3.30. Their IP Address Registers (0x3C-0x3F) .................................................................................. 39 7.3.31. PPP Control and Status Register (0x60)................................................................................... 40 7.3.32. PPP Interrupt Code (0x61) .......................................................................................................... 41 7.3.33. PPP Max Retry, (0x62) ................................................................................................................. 41 7.3.34. PAP String (0x64) ......................................................................................................................... 42 8. SERIAL PORT INTERFACE ........................................................................................................................ 43 8.1. OVERVIEW ................................................................................................................................................. 43 8.2. SERIAL PORT REGISTER MAP................................................................................................................... 43 8.2.1. Hardware Flow Control (RTS/CTS Handshaking)....................................................................... 44 8.2.2. Serial Port Control............................................................................................................................ 44 9. RESET FUNCTIONS ..................................................................................................................................... 45 9.1. OVERVIEW ................................................................................................................................................. 45 9.1.1. Hardware reset function.................................................................................................................. 45 9.1.2. Software reset function ................................................................................................................... 45 10. APPLICATION EXAMPLES ....................................................................................................................... 46 10.1.1. In case of x80 Family MPU with LCD Controller ....................................................................... 46 10.1.2. In case of 68k Family MPU with LCD Controller ....................................................................... 47 10.1.3. In case of Serial interface with LCD Controller .......................................................................... 48
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Hardware Specification
LIST OF FIGURES
FIGURE 2.-1 BLOCK DIAGRAM ..................................................................................................................... 3 FIGURE 3.-1 PIN ASSIGNMENT .................................................................................................................... 4 FIGURE 3.-2 PACKAGE DIMENSIONS ........................................................................................................... 5 FIGURE 3.-3 CONFIGURATION OF EACH PIN ................................................................................................. 7 FIGURE 5.-4 68 FAMILY MPU WRITE TIMING ............................................................................................ 11 FIGURE 5.-5 68 FAMILY MPU READ TIMING.............................................................................................. 12 FIGURE 5.-6 X80 FAMILY MPU WRITE CYCLE TIMING .............................................................................. 13 FIGURE 5.-7 X80 FAMILY MPU READ CYCLE TIMING ................................................................................ 14 FIGURE 5.-8 SERIAL INTERFACE WRITE TIMING......................................................................................... 15 FIGURE 5.-9 SERIAL INTERFACE READ TIMING ......................................................................................... 16 FIGURE 5.-1 INT1 INTERRUPT TIMING ....................................................................................................... 17 FIGURE 6.-1 MEMORY INTERFACE ARCHITECTURE.................................................................................... 18 FIGURE 8.-1 SERIAL DATA FORMAT ......................................................................................................... 43 FIGURE 9.-1 HARDWARE RESET TIMING..................................................................................................... 45 FIGURE 9.-2 SOFTWARE RESET TIMING .................................................................................................... 45 FIGURE 10.-1 EXAMPLE FOR X80 FAMILY MPU ......................................................................................... 46 FIGURE 10.-2 EXAMPLE FOR 68K FAMILY MPU ......................................................................................... 47 FIGURE 10.-3 EXAMPLE FOR SERIAL INTERFACE........................................................................................ 48
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Hardware Specification
LIST OF TABLES
TABLE 3.-1 PIN ASSIGNMENT ................................................................................................................................. 4 TABLE 3.-2 PIN DESCRIPTION ................................................................................................................................ 6 TABLE 4.-1 ABSOLUTE MAXIMUM RATINGS.................................................................................................. 8 TABLE 4.-2 RECOMMENDED OPERATING CONDITIONS ................................................................................. 8 TABLE 4.-3 DC CHARACTERISTICS ............................................................................................................. 9 TABLE 4.-4 POWER CURRENT CONSUMPTION ............................................................................................. 9 TABLE 5.-1 INTERFACE SELECTION ........................................................................................................... 10 TABLE 5.-2 CONNECTION RELATIONSHIP BETWEEN MPU AND PINS ........................................................... 10 TABLE 5.-3 68K FAMILY MPU WRITE CYCLE TIMING ................................................................................. 11 TABLE 5.-4 68K FAMILY MPU READ CYCLE TIMING.................................................................................. 12 TABLE 5.-5 X80 FAMILY MPU WRITE CYCLE TIMING ................................................................................ 13 TABLE 5.-6 X80 FAMILY MPU READ CYCLE TIMING.................................................................................. 14 TABLE 5.-7 SERIAL INTERFACE WRITE CYCLE TIMING .............................................................................. 15 TABLE 5.-8 SERIAL INTERFACE READ CYCLE TIMING ................................................................................ 16 TABLE 5.-9 INTERRUPT SELECTION TABLE ................................................................................................ 17 TABLE 6.-1 S-7600A MEMORY MAP (BANK 0).......................................................................................... 19 TABLE 6.-2 S-7600A MEMORY MAP (BANK 1).......................................................................................... 19 TABLE 7.-1 IAPI REGISTER MAP.............................................................................................................. 21 TABLE 7.-2 IAPI REGISTER MAP (CONTINUED)......................................................................................... 22 TABLE 7.-3 REVISION REGISTER BIT DEFINITIONS .................................................................................... 23 TABLE 7.-4 REVISION REGISTER DESCRIPTION ........................................................................................ 23 TABLE 7.-5 GENERAL CONTROL REGISTER BIT DEFINITIONS..................................................................... 23 TABLE 7.-6 GENERAL CONTROL REGISTER DESCRIPTION ......................................................................... 23 TABLE 7.-7 GENERIC SOCKET LOCATION REGISTER BIT DEFINITIONS ....................................................... 24 TABLE 7.-8 GENERIC SOCKET LOCATION REGISTER DESCRIPTION............................................................ 24 TABLE 7.-9 MASTER INTERRUPT REGISTER BIT DEFINITIONS .................................................................... 24 TABLE 7.-10 MASTER INTERRUPT REGISTER DESCRIPTIONS (CONTINUED)................................................ 25 TABLE 7.-11 CONF STATUS REGISTER BIT DEFINITIONS ........................................................................... 25 TABLE 7.-12 CONF STATUS REGISTER DESCRIPTION ............................................................................... 26 TABLE 7.-13 SERIAL PORT INTERRUPT REGISTER BIT DEFINITIONS............................................................ 27 TABLE 7.-14 SERIAL PORT INTERRUPT REGISTER DESCRIPTION ................................................................ 27 TABLE 7.-15 SERIAL PORT INTERRUPT MASK REGISTER BIT DEFINITIONS .................................................. 27 TABLE 7.-16 SERIAL PORT INTERRUPT MASK REGISTER DESCRIPTION ...................................................... 27 TABLE 7.-17 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X10)............................................................ 28 TABLE 7.-18 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X11)............................................................ 28 TABLE 7.-19 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X12)............................................................ 29 TABLE 7.-20 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X13)............................................................ 29 TABLE 7.-21 INDEX REGISTER BIT DEFINITION .......................................................................................... 29 TABLE 7.-22 INDEX REGISTER DESCRIPTION ............................................................................................. 29 TABLE 7.-23 SOCKET CONFIG STATUS LOW REGISTER BIT DEFINITIONS.................................................... 30 TABLE 7.-24 SOCKET CONFIG STATUS LOW REGISTER DESCRIPTION ........................................................ 31 TABLE 7.-25 SOCKET STATUS MID REGISTER BIT DEFINITIONS.................................................................. 32 TABLE 7.-26 SOCKET STATUS MID REGISTER DESCRIPTION ...................................................................... 32 TABLE 7.-27 SOCKET ACTIVATE REGISTER BIT DEFINITIONS...................................................................... 33 TABLE 7.-28 SOCKET ACTIVATE REGISTER DESCRIPTION .......................................................................... 33 TABLE 7.-29 SOCKET INTERRUPT REGISTER BIT DEFINITIONS ................................................................... 33 TABLE 7.-30 SOCKET INTERRUPT REGISTER DESCRIPTION........................................................................ 34 TABLE 7.-31 SOCKET DATA AVAIL REGISTER BIT DEFINITIONS .................................................................. 34 TABLE 7.-32 SOCKET DATA AVAIL REGISTER DESCRIPTION....................................................................... 34 TABLE 7.-33 SOCKET INTERRUPT MASK LOW REGISTER BIT DEFINITIONS.................................................. 35 TABLE 7.-34 SOCKET INTERRUPT MASK LOW REGISTER DESCRIPTION ...................................................... 35 TABLE 7.-35 SOCKET INTERRUPT MASK HIGH REGISTER BIT DEFINITIONS ................................................. 35 TABLE 7.-36 SOCKET INTERRUPT MASK HIGH REGISTER DESCRIPTION...................................................... 35 TABLE 7.-37 SOCKET INTERRUPT LOW REGISTER BIT DEFINITIONS ........................................................... 36 TABLE 7.-38 SOCKET INTERRUPT LOW REGISTER DESCRIPTION................................................................ 36 TABLE 7.-39 SOCKET INTERRUPT HIGH REGISTER BIT DEFINITIONS........................................................... 36
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Hardware Specification
TABLE 7.-40 SOCKET INTERRUPT HIGH REGISTER DESCRIPTION ............................................................... 37 TABLE 7.-41 THEIR PORT REGISTER BIT DEFINITIONS (0X36).................................................................... 38 TABLE 7.-42 THEIR PORT REGISTER BIT DEFINITIONS (0X37).................................................................... 38 TABLE 7.-43 OUR PORT REGISTER BIT DEFINITIONS (0X38) ...................................................................... 38 TABLE 7.-44 OUR PORT REGISTER BIT DEFINITIONS (0X39) ...................................................................... 38 TABLE 7.-45 SOCKET STATUS HIGH REGISTER BIT DEFINITIONS................................................................ 38 TABLE 7.-46 SOCKET STATUS HIGH REGISTER DESCRIPTION .................................................................... 39 TABLE 7.-47 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3C)......................................................... 39 TABLE 7.-48 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3D)......................................................... 39 TABLE 7.-49 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3E) ......................................................... 39 TABLE 7.-50 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3F) ......................................................... 39 TABLE 7.-51 PPP CONTROL AND STATUS REGISTER BIT DEFINITIONS (0X60)............................................ 40 TABLE 7.-52 PPP CONTROL STATUS REGISTER DESCRIPTION .................................................................. 40 TABLE 7.-53 PPP INTERRUPT CODE REGISTER BIT DEFINITIONS............................................................... 41 TABLE 7.-54 PPP INTERRUPT ERROR CODES ........................................................................................... 41 TABLE 7.-55 PPP MAX RETRY REGISTER ................................................................................................. 41 TABLE 7.-56 PAP STRING FORMAT .......................................................................................................... 42 TABLE 7.-57 PAP STRING EXAMPLE......................................................................................................... 42 TABLE 8.-1 SERIAL PORT REGISTER MAP ................................................................................................ 43
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S-7600A
Hardware Specification
1.
1.1.
Introduction
Product Overview
The S-7600A is a LSI that integrates TCP/IP network stack. It offers your devices a quicker and easier connectivity to a network with its on-chip serial interface and a static RAM that operates as a buffer. Implementing this LSI into your system can significantly reduce your software development cost. Also its low operating frequency gives benefits to the power consumption. TM The S-7600A also supports a microprocessor interface via the iReady iAPI register set, and connection to Physical Transport Layer Interface. iAPI consists of a set of register and operating definitions that allow any micro controller system to interface with the internal modules.
1.2.
Features
Industry standard protocols support : TCP/IP (Ver. 4.0) PPP (STD-51-compliant) UDP General purpose sockets : Configured for two sockets MPU interface : 68k/x80(MOTO/Intel) bus interface or Synchronous serial interface Physical Transport Layer Interface : Universal Asynchronous Receiver/Transmitter (UART) Low clock rate : Multiplied four by the bit-rate Operating frequency : 256kHz typical Low power consumption : Full-transmitting Operating current consumption : 0.9mA typ. Non-transmitting Operating current consumption : 150A typ. Standby current consumption : 1.0A typ. Stand-by mode : held by RESET signal Wide operating voltage range : 2.4V to 3.6V Easier application development : TM portable iAPI support

1.3.
Benefits
Off-loads MIPS allowing system to operate with low end and low cost processors. Consumes minimal power-up to 1/100 of competing solution.

Seiko Instruments Inc.
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S-7600A
Hardware Specification
1.4.
Trademarks
TM TM
iReady iAPI and iAPI is a trademark of iReady Corporation. All other products and brand names are trademarks and registered trademarks of their respective companies.
1.5.
Definitions
IP PPP TCP UDP API Internet Protocol Point-to-Point Protocol Transmission Control Protocol User Datagram Protocol Application Programming Interface

1.6.
Applicable Documents
S-7600A Functional Specification S-7600A API Application Manual

1.7.
1.
Cautions
DO NOT apply a voltage or current that exceeds the absolute maximum ratings to terminals. If applied, the IC may malfunction or be destroyed. The standard values are set with sufficient margins, but use the IC within the recommended operating conditions to optimize device quality. Measures against static electricity When transporting or storing ICs, use conductive containers or metal coated boxes. Check that there is no current leakage in electrical facilities, and be sure to ground them. Also ensure that workbenches and people who handle ICs are grounded. Excessive external noise to the power supply or I/O terminals of CMOS ICs causes latch-up, leading to faults and damage. If latch-up has occurred, immediately turn off the device, eliminate the cause, and turn on the device again. Keep the IC away from mechanical vibration, shock, and sudden changes in temperature. These may cause wires to break. Environment Use and store ICs below the absolute maximum rated temperature. DO NOT use or store ICs where condensation can occur. DO NOT use ICs where they are directly exposed to dust, salt, or acid gas such as SO 2. These may cause leaks between element leads and cause corrosion. To store ICs for a long time, DO NOT process them. During storage, DO NOT apply any load to ICs.
2.

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Seiko Instruments Inc.
S-7600A
Hardware Specification
2.
Functional Block Diagram
Figure 2-1 shows a functional block diagram of the S-7600A. There are blocks of the Network Stack and other functions related to it. The S-7600A has the interface for a host MPU and a Physical layer for various data terminal equipment.
SD(7:0) CS PSX C86 RS READX WRITEX BUSYX INTCTL INT1 INT2X
Network Stack
UDP TCP
SRAM Interface
MPU Interface
SRAM
10Kbytes
IP
PPP
CLK
RESETX
Physical Layer Interface
16-byte 1-byte FIFO BUFFER S2P P2S
Figure 2-1
The transport and network layers contain: Two general sockets that provide connectivity between the application layer and the transport layer. TCP/UDP module that allows for reliable (retransmission) and unreliable (no retransmission) datagram deliveries. IP module that provides connectionless packet delivery. PPP module that provides point-to-point connection link between two hosts.
DSRX RTSX RXD RI DCD DTRX TXD CTSX
Block diagram
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S-7600A
Hardware Specification
3. 3.1.
Terminals
Pin Assignment
36 INTCTRL WRITEX BUSYX READX INT2X
25
INT1
VSS
PSX
C86
37
SD7 NC TI2 SD6 TI1 VDD SD5 SD4 SD3 SD2 SD1
TI3
CS
RS
TI4 TI5 TI6 TI7 VDD TO1 TO2 TO3 TO4 TO5 TO6 TO7
24
48
SD0
13
RESETX
DSRX
DTRX
CTSX
RTSX
TEST
DCD
RXD
CLK
1
Figure 3-1Pin Assignment
Figure 3-1 shows Pin Assignment in Package. Table 3-1 shows signal names, listed by Pin Number. Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Pin name RESETX TEST CLK VSS CTSX DSRX RI RXD DCD DTRX RTSX TXD Pin No. 13 14 15 16 17 18 19 20 21 22 23 24
Table 3-1
Pin name TO7 TO6 TO5 TO4 TO3 TO2 TO1 VDD TI7 TI6 TI5 TI4
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36
TXD 12
VSS
RI
Pin name TI3 RS CS C86 READX VSS PSX WRITEX INTCTRL INT1 INT2X BUSYX
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48
Pin name SD7 NC TI2 SD6 TI1 VDD SD5 SD4 SD3 SD2 SD1 SD0
Pin Assignment
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Seiko Instruments Inc.
S-7600A
Hardware Specification
3.2.
Package Dimensions
S-7600A is housed in a 48-pin QFP package with 0.5mm pin pitch spacing. The package layout is depicted in Figure 3-2.
9.00.3 7.0
36 25
37
24
9.00.3
7.0
48
13
0.50.3
12
1
0.15
+0.10 -0.06
1.400.2 0
0.50
0~ 0.20
+0.1 0 0.20 -0.0 5
1.7m ax.
UN IT :m m
Figure 3-2
Package Dimensions
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S-7600A
Hardware Specification
3.3.
Pin Description
The pins and signal descriptions are listed by function in Table 3-2. Name VDD1,VDD2 VSS1,VSS2 RESETX TEST, TI1 to TI7 TO1 to TO7 CLK CTSX DSRX RI RXD DCD DTRX RTSX TXD RS CS C86 I/O Description - Positive power supply - GND potential I Reset input I Test input (pull-down resistor is built in) When normal use, connect to VSS or open O Test output When normal use, connect to Vss or open I Clock input I Clear to send input I Data set ready input I Ring indicator input I Serial received data input I Data carrier detect input O Data terminal ready output O Request to send output O Serial transmit data output I Register selection input I Chip selection input I MPU interface mode selection input 68k mode : 1 x80 mode : 0 I x80 mode : read requirement input 68k mode : enable input I parallel/serial interface selection input I x80 mode : write requirement input 68k mode : read/write selection input I INT1/INT2X drive type(CMOS/OD) selection input *OT Interrupt output(active High) from S-7600A chip to MPU *OT Interrupt output(active Low) from S-7600A chip to MPU O busy indicator output *B x80/68k mode : data bus Serial mode : serial data input *B x80/68k mode : data bus Serial mode : serial clock input *B x80/68k mode : data bus Serial mode : serial data output *B Data bus *OT : Tri-state output *B : bi-directional
Table 3-2 Pin Description
Type
A B D C C C C C C D D D C C C
READX PSX WRITEX INTCTRL INT1 INT2X BUSYX SD7 SD6 SD5 SD0 to SD4
C C C C E E D F F F F
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Seiko Instruments Inc.
S-7600A
Hardware Specification
3.4.
Pin Configuration
Figure 3-3 shows configuration of each pin.
A
pad cin
B
pad
Vss
C
pad cin
D
pad in
E
pad in
F
cIn pad in
oen
oen
Figure 3-3
Configuration of Each pin
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S-7600A
Hardware Specification
4.
4.1.
Electrical Characteristics
Absolute Maximum Ratings
Parameter Storage temperature Operating temperature Power supply voltage Input voltage Output voltage
Table 4-1
Symbol Tsta Topr VDD VIN VOUT
Conditions
Rating -40 to +125 -10 to +70
Unit
C C
Ta=25C Ta=25C Ta=25C
-0.3 to +4.0 VSS-0.3 to VDD+0.3 VSS to VDD
V V V
Absolute Maximum Ratings
4.2.
Recommended Operating Conditions
Parameter Operating Frequency range Symbol FOPR Conditions Ta=-10 to +70C Min. Typ. 0.256 Max. 5 Unit MHz Note 1
Clock Pulse width Operating voltage range Input voltage
Pw
Ta=-10 to +70C
80
-
-
nS
VDD
Ta=-10 to +70C
2.4
-
3.6
V
VIN
Ta=-10 to +70C
0
-
VDD
V
Note1: The clock is given by the CLK pin and needs to be as four times or more fast as the BAUD rate. (The multiplier is an integer whose tolerance is <2%)
Table 4-2
Recommended Operating Conditions
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Seiko Instruments Inc.
S-7600A
Hardware Specification
4.3.
DC Characteristics
Parameter Low level input voltage High level input voltage Low level input leakage current High level input leakage current High level input current Low level output current High level output current Schmitt Hysteresis voltage
Table 4-3 DC Characteristics
Symbol VIL
Unless otherwise specified: VDD=3.0V, VSS=0V, Ta=25C Conditions Min. Typ. Max. Unit 0.2 VDD V
VIH
-
0.8 VDD 1.0
V
ILL
VIN=VSS
-1.0
-
A
ILH
All input terminals without pull-down resister VIN=VDD
-1.0
-
1.0
A
IIH
All input terminals with pull-down resister VIN=VDD
18
70
220
A
IOL
VOL=0.4V
5.0
-
-
mA
IOH
VOH=2.6V
-
-
-3.5
mA
VWD
-
0.46
-
V
4.4.
Power Current Consumption
Parameter Full-transmitting Operating current consumption Non-transmitting Operating current consumption Standby current consumption Symbol IDD1 Unless otherwise specified: VDD=3.0V, VSS=0V, Ta=25C Conditions Min. Typ. Max. Unit Ta=-10 to +70C FOPR=256KHz IDD2 Ta=-10 to +70C FOPR=256KHz RESETX=VSS Is Ta=-10 to +70C 1.0 15.0 A 150 300 A 0.9 2.2 mA
Table 4-4
Power Current Consumption
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Hardware Specification
5.
5.1.
MPU Interface
Overview
The S-7600A supports two MPU interfaces: parallel and serial. In parallel interface mode, S-7600A can interface with x80 Family MPU or 68k Family MPU.
PSX CS RS READ X H: parallel x80 H: parallel 68k L: serial Table 5-1 Interface Selection CS RS H or L R/WX BUSYX H or L SI SCL SO Hi-Z CS RS CS RS READ X E R/WX BUSYX H D7 D6 D5 D4 to D0 WRITEX BUSYX L D7 D6 D5 D4 to D0 WRITEX BUSYX C86 SD7 SD6 SD5 SD4 to SD0
5.2.
Parallel Interface
Setting PSX to "H" select the parallel interface. In parallel interface mode the S-7600A can interface with either x80 Family MPU or 68k Family MPU. The desired MPU mode can be selected by setting the C86 pin to "H" or "L". RS 68k Family MPU R/WX READX 1 1 0 0 1 0 1 0
Table 5-2
x80 Family MPU WRITEX 1 0 1 0
Function
0 1 0 1
Read Register Write Register Read Index Register Write Index Register
Connection Relationship between MPU and Pins
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S-7600A
Hardware Specification
5.2.1.
68k Family MPU Mode
This mode can be selected by pulling the C86 input pin "H" and the PSX input pin "H". In this mode, the address and data are muxed into a single 8-bit bus. All cycles start by placing an address on the bus and setting the RS pin to "L". In this mode WRITEX signal works as read/write(R/WX) signal and READX is the enable(E) signal for 68k Family MPU interface. After the address cycle, the MPU generates a read or writes strobe by setting the READX and WRITEX pins. The S-7600A MPU interface logic assert a BUSYX signal low during data write and read phases. The MPU samples the BUSYX signal before starting a new cycle. The CPU can initiate a new cycle if the bit is "H".
5.2.1.1.
CS
Write Cycle Timing
RS
WRITEX (R/WX)
TAW6
TEW
TAH6 TCYC6
TAW6
TEW
TAH6
READX (E) TDS6 TDH6 SD7 to 0 Adress Data TDS6 TDH6
BUSYX TBD6 TBC6 TBOD6
CLK
Figure 5-4
68 Family MPU Write Timing
Symbol TCYC6 TAH6 TAW6 TDS6 TDH6 TEW TBD6 TBC6 TBOD6 NOTES:
Description System Cycle Time Address Hold Time Address Setup Time Data Setup time Data Hold Time Enable Pulse Width BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time

Min 100 ns 20ns 20ns 20ns 20 ns 40 ns 2CLK -
Max 1.9CLK 30ns 30ns
Notes
CL=80pF CL=80pF
CLK is the clock of S-7600A Timing is specified of 50% of the signal waveform. Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Table 5-3
68k Family MPU Write Cycle Timing
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Hardware Specification
5.2.1.2.
CS
Read Cycle Timing
RS TAW6 WRITEX (R/WX)
TEW TAH6
TAW6
TEW TCYC6
TAH6
TAW6
TEW
TAH6
READX (E) TDS6 SD7 to 0 Adress TDH6 TACC6 Adress TOH6 TACC6 Data TOH6
BUSYX TBD6 CLK TBC6
TBOD6
Figure 5-5
68 Family MPU Read Timing
Symbol TCYC6 TAH6 TAW6 TDS6 TDH6 TACC6 TOH6 TEW TBD6 TBC6 TBOD6
Description System Cycle Time Address Hold Time Address Setup Time Data Setup time Data Hold Time Access time Output Disable Time Enable Pulse Width BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time

Min 100 ns 20ns 20ns 20ns 20 ns 20 ns 40 ns 2CLK -
Max 30ns 1.9CLK 30ns 3CLK 30ns
Notes
CL=80pF CL=80pF CL=80pF CL=80pF
NOTES:
CLK is the clock of S-7600A Timing is specified of 50% of the signal waveform. Rise/fall time(20%,80%) of the input signal is 15nsec or less.
68k Family MPU Read Cycle Timing
Table 5-4
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5.2.2.
x80 Family MPU Mode
This mode is selected by pulling the C86 input pin "L" and the PSX input pin "H". In this mode, the address and data are muxed onto a single 8-bit bus. All cycles start with the address placed on the bus. This address is then latched internally on the rising edge of WRITEX. The RS pin "L" indicates that the WRITEX strobe is for the address phase. In the next phase, data is either written or read by generating WRITEX or READX strobe. The MPU interface logic will assert the BUSYX signal after READX or WRITEX strobes are de-asserted. The BUSYX signal is de-asserted after the S-7600A complete a read or writes operation. The MPU samples the BUSYX signal before starting a new cycle. The MPU can initiate a new cycle after the BUSYX signal gets de-asserted.
5.2.2.1.
CS
Write Cycle Timing
RS
READX
TAW8
TCC8
TAH8 TCYC8
TAW8
TCC8
TAH8
WRITEX TDS8 TDH8 SD7 to 0 Adress Data TDS8 TDH8
BUSYX
TBD8
TBC8
TBOD8
CLK
Figure 5-6
x80 Family MPU Write Cycle Timing
Symbol TCYC8 TAH8 TAW8 TDS8 TDH8 TCC8 TBD8 TBC8 TBOD8 NOTES:

Description System Cycle Time Address Hold Time Address Setup Time Data Setup time Data Hold Time Control Pulse Width BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time CLK is the clock of S-7600A
Min 100 ns 20ns 20ns 20ns 20 ns 40 ns 2CLK -
Max 1.9CLK 30ns 30ns
Notes
CL=80pF CL=80pF
Timing is specified of 50% of the signal waveform. Rise/fall time(20%,80%) of the input signal is 15nsec or less.
x80 Family MPU Write Cycle Timing
Table 5-5
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5.2.2.2.
CS
Read Cycle Timing
RS TAW8 READX TAW8
TCC8
TAH8
TCC8 TCYC8
TAH8
TAW8
TCC8
TAH8
WRITEX
TDS8 SD7 to 0 Adress
TDH8 TACC8 Adress TOH8 TACC8 Data TOH8
BUSYX
TBD8
TBC8
TBOD8
CLK
Figure 5-7
x80 Family MPU Read Cycle Timing
Symbol TCYC8 TAH8 TAW8 TDS8 TDH8 TACC8 TOH8 TCC8 TBD8 TBC8 TBOD8 NOTES:
Description System Cycle Time Address Hold Time Address Setup Time Data Setup time Data Hold Time Access time Output Disable Time Control Pulse Width BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time

Min 100 ns 20ns 20ns 20ns 20 ns 20 ns 40 ns 2CLK -
Max 30ns 1.9CLK 30ns 30ns
Notes
CL=80pF CL=80pF CL=80pF CL=80pF
CLK is the clock of S-7600A Timing is specified of 50% of the signal waveform. Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Table 5-6
x80 Family MPU Read Cycle Timing
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5.3.
Serial Interface
This mode is selected by pulling the PSX input pin "L". In this mode Bit 6 of the Data Bus is used as the serial clock and bit 5 and 7 are used as Data Input and Data Output. Bit 0 to 4 are high impedance. By pulling WRITEX signal to "H" or "L", the MPU performs a read or write operation.
5.3.1.
CS
Write Cycle Timing
RS
WRITEX (R/WX)
TASS TCYCS
TAHS
TASS
TAHS
SD6 (SCL) TCLLS SD7 (SI)
A7 A6 A5
TCLHS
A4 A3 A2
TDSS
A1 A0
TDHS
D7 D6 D5 D4 D3 D2 D1 D0
BUSYX TBDS TBCS TBODS CLK
Figure 5-8
Serial Interface Write Timing
Symbol TCYCS TCLLS TCLHS TASS TAHS TDSS TDHS TBDS TBCS TBODS NOTES:

Description System Cycle Time Clock L Time Clocl H Time Address Setup Time Address Hold Time Data Setup time Data Hold Time BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time
Min 100 ns 40ns 40 ns 20ns 20ns 20ns 20 ns 2CLK -
Max 1.9CLK 30ns 30ns
Notes
CL=80pF CL=80pF
CLK is the clock of S-7600A Timing is specified of 50% of the signal waveform. Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Serial Interface Write Cycle Timing
Table 5-7
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5.3.2.
CS
Read Cycle Timing
RS
T ASS WRITE X T CYCS T CLH
T AHS
T ASS
T AHS
T ASS
T AHS
SD6 T CLLS
A7 A6 A5 A4 A3
T DSS
A2 A1 A0
T DHS
T OHS
T DDS
T OHS
SD7
T DDS
SD5
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
T BD BUSYX
T BCS
T BODS
CLK
Figure 5-9
Serial Interface Read Timing
Symbol TCYCS TCLLS TCLHS TASS TAHS TDSS TDHS TDDS TOHS TBDS TBCS TBODS NOTES:
Description System Cycle Time Clock L Time Clocl H Time Address Setup Time Address Hold Time Data Setup time Data Hold Time Data delay Time Output Disable Time BUSYX Delay Time BUSYX Pulse Width BUSYX Output Disable Time

Min 100 ns 40ns 40 ns 20ns 20ns 20ns 20 ns 2CLK -
Max 1.9CLK 30ns 20ns 30ns 30ns
Notes
CL=80pF CL=80pF CL=80pF CL=80pF
CLK is the clock of S-7600A Timing is specified of 50% of the signal waveform. Rise/fall time(20%,80%) of the input signal is 15nsec or less.
Serial Interface Read Cycle Timing
Table 5-8
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5.4.
Interrupt
The interrupt signal outputs an active level while the interrupt flag is set in the interrupt register in the S-7600A's interrupt register. The interrupt signal returns to an inactive level if the flag clears. Show the interrupt timing in the Figure 5-1. The INT1 and INT2X can be Open Drain or CMOS output depending on the setting of INTCTL. The INT1 and INT2X outputs are CMOS if INTCTL is "H" otherwise outputs are Open Drain. Table 5-9 defines the interrupt selection. Interrupt flag Set Set Reset Reset
Table 5-9
INTCTL H L H L
Interrupt Selection Table
INT1 H H L Hi-Z
INT2X L L H Hi-Z
CS
RS
WRITEX
SD7 to 0
Adress
Data
BUSYX
CLK
INT1
Clear interrupt (x80 Family MPU mode, INTCTL=high)
Figure 5-1 INT1 interrupt timing
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6.
6.1.
Memory Requirements
Overview
S-7600A contains too general sockets along with the TCP/UDP/IP and PPP protocols. Their total memory requirement is 10K bytes. This memory is included on the S-7600A chip.
6.2.
Memory Interface Architecture
The Network Stack feeds all of its memory requests into a single Memory Arbiter inside of the Network Stack core. The arbiter then feeds out one memory request to the SRAM interface. This interface serves to translate the network stack's timing into signal timing required by the SRAM. This architecture is shown in Figure 6-1.
Network Stack
TCP / UDP Memory Arbiter SRAM Interface
IP
SRAM
PPP
Serial Port
Figure 6-1 Memory Interface Architecture
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6.3.
Memory Map
A custom memory map is generated to compact the size of the SRAM required to support S-7600A. S7600A has two 5K byte memory banks (0 and 1). This mapping is as shown in Table 6-1 and Table 62.
Table 6-1 S-7600A Memory Map (Bank 0)
Address 0x0000 - 0x07FF 0x0800 - 0x0BFF 0x0C00 - 0x0FFF 0x1000 - 0x13FF
Size 2K 1K 1K 1K
Contents Socket 0 Receive Buffer Socket 0 Send Buffer TCP Data Base IP Buffer
Table 6-2
S-7600A Memory Map (Bank 1)
Address 0x0000 - 0x07FF 0x0800 - 0x0BFF 0x0C00 - 0x0FFF 0x1000 - 0x13FF
Size 2K 1K 1K 1K
Contents Socket 1 Receive Buffer Socket 1 Send Buffer PPP Buffer PAP Buffer
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7.
7.1.
S-7600A Register Definitions
Overview
This section covers the S-7600A's API registers. The register are divided into three types: global, direct and indexed. Global registers occupy the address space from 0x00 to 0x1D and 0x60 to 0x6F. Direct and indexed registers occupy the configuration space from 0x20 to 0x3F. Indexed register require the socket index to be set prior to accessing the registers.
7.2.
iAPI Register Map
Table 7-1 and Table 7-2 shows the complete iAPI register map for the S-7600A chip. All registers not listed are reserved, and should not be accessed.
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Table 7-1
iAPI Register Map
Add 0x00 0x01 0x02
Register Revision General_Control General_Socket_ Location
Bit Definitions Major Revision Number 0 0 0 0 Minor Revision Number 0 0 S1 SW_ RST S0
0x04 0x08
Master_Interrupt Serial_Port_Config
S_ DA V
DCD
DSR/ HWFC
CTS
RI
PT_ INT
LINK _INT
SOCK _INT SCTL
DTR
RTS
0x09 0x0A
Serial_Port_Int Serial_Port_Int_ Mask
PT_ INT
PINT _EN
DSINT_ EN
-
-
-
-
-
-
0x0B 0x0C 0x0D 0x10 - 0x13 0x1C 0x1D 0x20 0x21 0x22 0x23 0x24 0x26 0x28
NOTE:
Serial_Port_Data BAUD_Rate_Div Our_IP_Address Clock_Div_Low Clock_Div_High Index TOS* Socket_ Config_Status_Low* Socket_Status_Mid* Socekt_Activate Socket_Interrupt Socket_Data_Avail
Serial Data Register BAUD Rate Divider Registers Our IP Address Low Byte for 1 kHz clock divider High Byte for 1 kHz clock divider Socket index Type of Service Field
TO
Buff_ Empty RST Buff_ Full Term Data_ Avail/ RST ConU
-
Protocol_Type TCP State
URG
-
-
-
-
-
S1 I1 DAV1
S0 I0 DAV0
1)Reserved bits are signified by a dash (-). All reserved bits should be written as "0". 2)Indexed registers are signified by an asterisk (*).
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Table 7-2
iAPI Register Map (Continued)
Add 0x2A 0x2B 0x2C 0x2D 0x2E 0x30 0x30 - 0x31 0x32 - 0x33 0x34 - 0x35 0x36 - 0x37 0x38 - 0x39 0x3A 0x3C - 0x3F 0x60 0x61 0x62 0x64
NOTE:
Register Socket_Interrupt_ Mask_Low* Socket_Interrupt_ Mask_High* Socket_Interrupt_Low* Socket_Interrupt_High* Socket_Data* TCP_Data_Send (WO)* Buffer_Out (RO)* Buffer_In (RO)* Urgent_Data_Pointer* Their_Port* Our_Port* Socket_Status_High* Their_IP_Address* PPP_Control_Status PPP_Interrupt_Code PPP_Max_Retry PPP_String TO_ En
URG_En Buff_ Emp_ En RST_ En Buff_ Empty
Bit Definitions
Buff_F ull Term_ En Buff_ Full Data_ Avail_ En ConU En Data_ Avail
-
-
-
-
TO URG
RST
Term
ConU
Socket 8-bit data Any write causes data to be sent Buffer Out Length Buffer In Length Urgent Data Offset Pointer, UDP Datagram Size Target Port Address Our Port Address Snd _bsy
Target IP Address
PPP_Int Con_ Val Use_ PAP To_ Dis PPP_ Int_En Kick PPP_ En PPP_ Up / SRset
Interrupt Code Pap user name and password PPP Maximum retry
1)Reserved bits are signified by a dash (-). All reserved bits should be written as "0". 2)Indexed registers are signified by an asterisk (*).
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7.3. 7.3.1.
Register Definitions Revision Register (0x00)
(Read-Only, Default 0x2110)
This direct read-only register reports back the design revision. See the design revision form in Table 73 and Table 7-4.
Table 7-3 Revision Register Bit Definitions
Bit Def. Default
Table 7-4
7
6
5
4
3
2
1
0
Major Revision Number 0x21
Revision Register Description
Minor Revision Number 0x10
Bit 7:4 3:0
Bit Name Major Revision Number Minor Revision Number
Access R R
Description This nibble indicates the major revision number for the S-7600A core. This nibble indicates the minor revision number for the S-7600A core.
7.3.2.
General Control Register (0x01)
(Read/Write, Default 0x00)
This direct register contains the master software reset. See the register format in Table 7-5 and Table 7-6.See the wave format in figure 9.-2.
Table 7-5 General Control Register Bit Definitions
Bit Def. Default
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 SW_RST 0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0". Table 7-6 General Control Register Description
Bit 0
Bit Name SW_RST
Access R/W Software Reset.
Description
This active high reset returns the S-7600A core to power-on reset settings. It is self-clearing and does not need to be written to "0" for proper operations. 0 = Normal operation 1 = Soft reset
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7.3.3.
(Read-Only)
Generic Socket Location Register (0x02)
This register is used to report back the location of general sockets to the software layer. Only bits [1:0] will be set because the S-7600A chip is equipped with two general sockets.
Table 7-7 Generic Socket Location Register Bit Definitions
Bit Def. Value
Table 7-8
7 S7 0
6 S6 0
5 S5 0
4 S4 0
3 S3 0
2 S2 0
1 S1 1
0 S0 1
Generic Socket Location Register Description
Bit 7 6 5 4 3 2 1 0
Bit Name S7 S6 S5 S4 S3 S2 S1 S0
Access R R R R R R R R Not available Not available Not available Not available Not available Not available
Description
General socket 1 available General socket 0 available
7.3.4.
Master Interrupt (0x04)
(Read-Only, Default 0x00)
This direct register indicates the source of the S-7600A interrupt.
Table 7-9 Master Interrupt Register Bit Definitions
Bit Def. Default
7 0
6 0
5 0
4 0
3 0
2
PT_INT
1
LINK_INT
0
SOCK_INT
0
0
0
NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as "0".
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Table 7-10
Master Interrupt Register Descriptions (Continued)
Bit 2
Bit Name PT_INT
Access R
Description Physical Transport Interrupt The physical transport triggers this interrupt. An application should check the Serial Port Int register to determine the actual cause of the interrupt.
1
LINK_INT
R
Link Layer Interrupt The link layer triggers this interrupt. An application should check the PPP Interrupt Code register to determine the actual cause of the interrupt.
0
SOCK_INT
R
Socket Interrupt One of the sockets that need servicing causes this interrupt. An application should check the Socket Interrupt register to determine the actual socket number.
7.3.5.
Serial Port Configuration / Status Register (0x08)
(Read/Write, Default 0X0XX110B)
This register configures the serial port as shown in Table 7-11 and Table 7-12.
Table 7-11 Conf Status Register Bit Definitions
Bit Def. Default
7 S_DAV 0
6 DCD -
5 DSR/ HWFC 0
4 CTS -
3 RI -
2 DTR 1
1 RTS 1
0 SCTL 0
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Table 7-12 Conf Status Register Description
Hardware Specification
Bit 7 S_DAV
Bit Name
Access R/W
Description Serial Port Data Available When read, bit indicates that Serial Port data is available. This bit should be written 0.
6
DCD
R/W
Carrier Detect This bit reflects the current state of the DCD bit on the serial port. It is independent of the SCTL bit setting. This bit should be written 0.
5
DSR / HWFC
R/W
Data Send Ready / Hardware Flow Control When read, this bit reflects the current state of the DSR bit on the serial port. When this bit written: 0 = Hardware Flow control is deactivated 1 = Hardware Flow control activated Refer to Chapter 8 for more information about Hardware Flow Control.
4
CTS
R
Clear To Send This read-only bit reflects the current state of the CTS bit on the serial port. It is independent of the SCTL bit setting.
3
RI
R
Ring Indicator This read-only bit reflects the current state of the RI bit on the serial port. It is independent of the SCTL bit setting.
2
DTR
R/W
Data Terminal Ready Reading this bit follows the current state of the DTR bit on the serial port. The MPU can control the DTR by writing to this bit.
1
RTS
R/W
Request To Send Reading this bit follows the current state of the RTS bit on the serial port. The MPU can control the RTS by writing to this bit.
0
SCTL
R/W
Serial Port Control This bit determines who controls the serial port. When this bit is low (default), the MPU controls the port. When the SCTL bit is high, the network stack controls the serial port. 0 = MPU controls port 1 = Hardware controls port
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7.3.6.
Serial Port Interrupt Register (0x09)
(Read-Only, Default 0X000000B)
This register indicates the state of the serial port interrupt.
Table 7-13 Serial Port Interrupt Register Bit Definitions
Bit Def. Default
7 PT_INT 0
6 -
5 0
4 0
3 0
2 0
1 0
0 0
NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as "0". Table 7-14 Serial Port Interrupt Register Description
Bit 7
Bit Name PT_INT
Access R
Description Port Transport Interrupt This bit indicates when the serial port interrupt is active. This condition depends on the states of the PINT_EN and DSINT_EN bits in the Serial Port Interrupt Mask Register. When PINT_EN is 1, an interrupt will occur whenever data is available in the serial port input FIFO ("S_DAV" in the Serial Port Configuration/Status Register is 1). When DSINT_EN is 1, an interrupt will be active whenever the CPU can write to the Serial Port Data Register to transmit a byte of data. If both PINT_EN and DSINT_EN are enabled, the interrupt will be active if either condition is met.
7.3.7.
Serial Port Interrupt Mask Register (0x0A)
(Read/Write, Default 0x00)
This register enables the serial port interrupts. The default for this register is 0x00 (interrupts disabled).
Table 7-15 Serial Port Interrupt Mask Register Bit Definitions
Bit Def. Default
7 PINT_EN 0
6 DSINT_EN 0
5 0
4 0
3 0
2 0
1 0
0 0
NOTE: Reserved bits are signified by a dash (-). All Reserved bits should be written as "0". Table 7-16 Serial Port Interrupt Mask Register Description
Bit 7
Bit Name PINT_EN
Access R/W
Description Port Interrupt Enable This is the enable for the port interrupt.
6
DSINT_EN
R/W
Data sent interrupt Enable. This is enable for the data sent interrupt.
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7.3.8.
(Read/Write)
Serial Port Data Register (0x0B)
This register sends data to and reads data from the serial port UART. The data is valid when the S_DAV bit in the Serial Port Config register is set. Data can be written to this register when the PT_INT bit in the Serial Port Interrupt register is set. See the register description in Table 7.-14.
Note: This register should only be used when the SCTL bit in the Serial Port config register is low.
7.3.9.
BAUD Rate Divider Registers (0x0C-0x0D)
(Read/Write, Default 0x0000)
These registers set the BAUD rate for the serial port. Calculate the value by using the following formula: Program Value = [(clk Frequency) / (BAUD Rate)] - 1 Where clk is the clock for the S-7600A core Example: The clock rate of the S-7600A is 256 KHz and a BAUD rate of 64 Kbps is desired, the programmed value should be: (256 KHz / 64 k) - 1 = 4 - 1 = 3
Note: The lowest value that should be programmed into these registers is 0x0003.
7.3.10.
Our IP Address Registers (0x10-0x13)
(Read/Write, Default 0x00000000)
These registers store our IP address or the IP address of the local device. The 0x10 register stores the least significant byte and the 0x13 register stores the most significant byte. If the system controller dose not write an IP address, it will be negotiated for during PPP negotiations (floating IP address). When a PPP connection is established (indicated by bit 0, register 60) these registers can be read to query the IP address obtained.
Table 7-17 Our IP Address Register Bit Definitions (0x10)
Bit Def. Default
Table 7-18
7
6
5
4 0x00
3
2
1
0
Least significant byte of the local IP address
Our IP Address Register Bit Definitions (0x11)
Bit Def. Default
7
6
5
4 0x00
3
2
1
0
3rd byte of the local IP address
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Table 7-19
Our IP Address Register Bit Definitions (0x12)
Bit Def. Default
Table 7-20
7
6
5
4 0x00
3
2
1
0
2nd byte of the local IP address
Our IP Address Register Bit Definitions (0x13)
Bit Def. Default
7
6
5
4 0x00
3
2
1
0
Most significant byte of the local IP address
7.3.11.
Clock Divider Registers (0x1C-0x1D)
(Read/Write, Default 0x03E7)
These registers program the 1kHz clock generator. This clock is used internally for various S-7600A timing functions. The following equation determines the value programmed into these registers: (clk Freq/1 kHz) - 1 = Divide Count Where clk Freq is S-7600A clock frequency. Therefore, for a 1 MHz clock, the divide count equals 1M / 1kHz - 1= 999 = 0x03e7.
7.3.12.
Index Register (0x20)
(Read/Write, Default 0x00)
This register must be programmed prior to accessing indexed socket registers. Valid programmed values are 0x00 and 0x01. If the socket number has not changed since the last access, this register not need to be reprogrammed.
Table 7-21 Index Register Bit Definition
Bit Def. Default
Table 7-22
7
6
5
4 0x00
3
2
1
0
Socket Index [7:0]
Index Register Description
Bit
7:0
Bit Name
Socket_Index
Access
R/W
Description
0x00 : General Socket 0 Selected 0x01: General Socket 1 Selected All other values are reserved
7.3.13.
Type of Service Register (TOS) (0x21)
(Read/Write, Default 0x00)
This register configures the TOS field in the IP header for outgoing datagrams. It is an optional setting that defaults to 0x00.
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7.3.14.
Socket Config Status Low Register (0x22)
(Read/Write, Default 0x00)
This register configures the socket.
Table 7-23 Socket Config Status Low Register Bit Definitions
Bit Def.
7 TO
6 Buff_ Empty
5 Buff_Full
4 Data_ Avail / RST
3 -
2
1
0
Protocol_Type
Default
0
0
0
0
0
0
NOTE: Reserved bits are signified by a dash ( - ). All reserved bits should be written as "0".
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Table 7-24 Socket Config Status Low Register Description
Hardware Specification
Bit 7 TO
Bit Name
Access R TCP Timeout
Description
This bit indicates that a TCP timeout condition occurred while attempting to establish a TCP connection or while waiting for a TCP packet after the connection was established. 0 = Normal Operating Condition 1 = Timeout Occurred 6 Buff_Empty R
This bit indicates whether or not a socket's outgoing data buffer is empty. The bit sets on an empty condition. It then clears and remains clear as long as there is any data in the socket's outgoing data buffer.
0 = Buffer Not Empty 1 = Buffer Empty 5 Buff_Full R This bit indicates whether space is available to write data. It also triggers an interrupt when the outgoing data buffer is full, and the Buff_Full_En bit in the Socket Interrupt Mask Low register (0x2A) is set. The Data Register should not be written to when this bit is a "1". 0 = Buffer Space Available 1 = No Buffer Space Available 4 Data_Avail / RST R/W Writing this bit resets all socket parameters to default settings. It is self-clearing and dose not need to be written to low for proper operations. Before resetting, ensure that Snd_Bsy bit of Socket Status High register (0x3A) is 0. When read, this bit indicates that the socket has data available. These bits are used to set the protocol of the socket. All decodes not shown are reserved. 010 = TCP Client Mode 101 = UDP Mode 110 = TCP Server mode
2:0
Protocol_Type
R/W
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7.3.15.
Socket Status Mid Register (0x23)
(Read-Only, Default 0x00)
This read-only register reports other socket status conditions.
Table 7-25 Socket Status Mid Register Bit Definitions
Bit Def. Default
Table 7-26
7 URG 0
6 RST 0
5 Term 0
4 ConU 0
3
2 0x0
1 TCP State
0
Socket Status Mid Register Description
Bit 7
Bit Name URG
Access R
Description
This bit indicates the arrival of urgent data. Writing a "1" to the URG bit in the Socket Interrupt register (bit 7) clears this bit. 0 = No urgent data present 1 = Urgent data present
6
RST
R
This bit indicates when the socket receives the RST signal from the TCP peer. 0 = No RST received 1 = RST received
5
Term
R
This bit indicates when the socket terminates from the source and triggers an interrupt if the Term_En bit is set in the Socket Interrupt Mask High register (0x2B). The interrupt mask setting does not effect the reporting of this status bit. 0 = Normal Operating Condition 1 = Socket terminated from source This bit becomes "1" when the S-7600A receives a TCP segment with the FIN flag on. This means that the remote peer has requested to close the TCP connection.
4
ConU
R
This bit indicates when the socket establishes a connection to a host machine. The bit clears when the connection terminates (by either end). 0 = No Connection Established 1 = Connection Established
3:0
TCP State
R
These bits indicate the current TCP state. 0 = CLOSED 1 = SYN_SENT 2 = ESTABLISHED 3 = CLOSE_WAIT 4 = LAST_ACK 5 = FIN_WAIT1 6 = FIN_WAIT2 7 = CLOSING 8 = TIME_WAIT 9 = LISTEN a = SYN_RECVD
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7.3.16.
Socket Activate Register (0x24)
(Read/Write, Default 0x00)
This register is used to activate the sockets and also show the current status of each socket. Setting a bit to "1" activates the corresponding socket. This register defaults to 0x00 upon resets.
Table 7-27 Socket Activate Register Bit Definitions
Bit Def. Default
Table 7-28
7 0
6 0
5 0
4 0
3 0
2 0
1 S1 0
0 S0 0
Socket Activate Register Description
Bit 1 S1
Bit Name
Access R/W
Description This bit is used to activate general socket 1. 0 = General socket 1 inactive 1 = General socket 1 active
0
S0
R/W
This bit is used to activate general socket 0. 0 = General socket 0 inactive 1 = General socket 0 active
7.3.17.
Socket Interrupt Register (0x26)
(Read-Only, Default 0x00)
This register indicates which socket has interrupts pending. When identification of an interrupting socket occurs, the actual source of the interrupt is determined by examining the specific socket's interrupt register.
Table 7-29 Socket Interrupt Register Bit Definitions
Bit Def. Default
7 0
6 0
5 0
4 0
3 0
2 0
1 I1 0
0 I0 0
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Table 7-30
Socket Interrupt Register Description
Bit 1 I1
Bit Name
Access R
Description This bit is used to indicate that socket 1 has an interrupt pending. 0 = General socket 1 interrupt inactive 1 = General socket 1 interrupt active
0
I0
R
This bit is used to indicate that socket 0 has an interrupt pending. 0 = General socket 0 interrupt inactive 1 = General socket 0 interrupt active
7.3.18.
Socket Data Available Register (0x28)
(Read-Only, Default 0x00)
This read-only register indicates which socket has data pending in the input buffer. A "1" in a bit position indicates that the socket has data available. The bit remains set as long as there is data available.
Table 7-31 Socket Data Avail Register Bit Definitions
Bit Def. Default
Table 7-32
7 0
6 0
5 0
4 0
3 0
2 0
1 DAV1 0
0 DAV0 0
Socket Data Avail Register Description
Bit 1 DAV1
Bit Name
Access R
Description This bit is used to indicate that socket 1 has data available. 0 = General socket 1 has no data available 1 = General socket 1 has data available
0
DAV0
R
This bit is used to indicate that socket 0 has data available. 0 = General socket 0 has data available 1 = General socket 0 has data available
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7.3.19.
Socket Interrupt Mask Low Register (0x2A)
(Read/Write, Default 0x00)
This register reports certain interrupt conditions. Setting a bit enables the corresponding interrupt.
Table 7-33 Socket Interrupt Mask Low Register Bit Definitions
Bit Def. Default
7 TO_En 0
6
Buff_ Emp_En
5 Buff_Full_En 0
4 Data_Avail_En 0
3 0
2 0
1 0
0 0
0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0". Table 7-34 Socket Interrupt Mask Low Register Description
Bit 7 6 5 4
Bit Name TO_En Buff_Empty_En Buff_Full_En Data_Avail_En
Access R/W R/W R/W R/W
Description Writing a "1" enables the Timeout interrupt. Writing a "1" enables the Buffer Empty interrupt. Writing a "1" enables the Buffer Full interrupt. Writing a "1" enables the Data Available interrupt.
7.3.20.
Socket Interrupt Mask High Register (0x2B)
(Read/Write, Default 0x00)
This register enables certain types of interrupt conditions. Setting bits enables their corresponding interrupts.
Table 7-35 Socket Interrupt Mask High Register Bit Definitions
Bit Def. Default
7 URG_En 0
6 RST_En 0
5 Term_En 0
4 ConU_En 0
3 0
2 0
1 0
0 0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0". Table 7-36 Socket Interrupt Mask High Register Description
Bit 7 6 5 4
Bit Name URG_En RST_En Term_En ConU_En
Access R/W R/W R/W R/W
Description Writing a "1" to enable the Urgent Data interrupt. Writing a "1" to enable the Connection Reset interrupt. Writing a "1" to enable the Socket Termination interrupt. Writing a "1" to enable the Connection Up interrupt.
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7.3.21.
Socket Interrupt Low Register (0x2C)
(Read/Write, Default 0x00)
This register reports certain interrupt conditions. When an interrupt condition occurs and its enable bit is set, the hardware sets the corresponding bit. Writing a "1" to the bit clears it. Disabling the corresponding enable bit prevents the interrupt from showing.
Table 7-37 Socket Interrupt Low Register Bit Definitions
Bit Def. Default
7 TO 0
6 Buff_Emplty 0
5 Buff_Full 0
4 Data_Avail 0
3 0
2 0
1 0
0 0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0". Table 7-38 Socket Interrupt Low Register Description
Bit 7 TO
Bit Name
Access R/W
Description This interrupt is generated when a timeout condition occurred while trying to establish a connection. Writing a "1" to this bit clears the interrupt. This interrupt is generated when outgoing buffer is empty. Writing a "1" to this bit clears the interrupt. This interrupt is generated when there is more buffer space available. Writing a "1" to this bit clears the interrupt. This interrupt is generated when data is available from the incoming buffer. Writing a "1" to this bit clears the interrupt.
6 5
Buff_Empty Buff_Full
R/W R/W
4
Data_Avail
R/W
7.3.22.
Socket Interrupt High Register (0x2D)
(Read/Write, Default 0x00)
This register reports certain interrupt conditions. When an interrupt condition occurs and its enable bit is set, the hardware sets the corresponding bit. Writing a "1" to the bit clears it. Disabling the corresponding enable bit prevents the interrupt from showing.
Table 7-39 Socket Interrupt High Register Bit Definitions
Bit Def. Default
7 URG 0
6 RST 0
5 Term 0
4 ConU 0
3 0
2 0
1 0
0 0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0".
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Table 7-40
Socket Interrupt High Register Description
Bit 7 URG
Bit Name
Access R/W
Description This interrupt is generated when urgent data arrives. The system interface should read the Urgent Data Pointer register to see the location of the data. Writing a "1" to this bit clears the interrupt. This interrupt is generated when a TCP peer sends the socket RST flag indicating that the current TCP session is not valid. Writing a "1" to this bit clears this interrupt. When this condition occurs, the hardware no longer operates and re-initializing the socket is recommended. This interrupt is generated when the socket connection is terminated and a TCP FIN flag is received. Writing a "1" to this bit clears the interrupt. This interrupt is generated when a connection is established. Writing a "1" to this bit clears the interrupt.
6
RST
R/W
5
Term
R/W
4
ConU
R/W
7.3.23.
Socket Data Register (0x2E)
(Memory Mapped Read/Write, Default 0x00)
This register is used by a system controller to read incoming data packets and write outgoing data. Data transmissions start for TCP connections only after a write occurs at 0x30.
7.3.24.
TCP Data Send and Buffer Out Length Registers (0x30 - 0x31)
(Read/Write, Default 0x03FF)
When read, these registers report the amount of space available in the outgoing buffer. Register 0x30 stores the least significant byte; 0x31 stores the most significant byte. Writing any data to 0x30 causes data transmissions to start on TCP connections.
7.3.25.
Buffer In Length Registers (0x32-0x33)
(Read-Only, Default 0x0000)
These read-only registers report the amount of data available in the received data buffer. 0x32 stores the least significant byte; 0x33 stores the most significant byte.
7.3.26.
Urgent Pointer / UDP Datagram Size Registers (0x34-0x35)
(Read-Only, Default 0x0000)
These read-only registers report the offset to the start of urgent data (as marked through the TCP header) relative to the incoming data buffer. Register 0x34 stores the least significant byte; 0x35 stores the most significant byte. When a socket is configured as a UDP socket, these registers indicate the size of the current UDP datagram. The least significant byte is stored in 0x34 and the most significant byte is stored in 0x35.
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7.3.27.
Their Port Registers (0x36-0x37)
(Read/Write, Default 0x0000)
These registers specify the destination port for an outgoing data packets. For client mode, this value must be set prior to activating the socket. For TCP server mode, these register are automatically setup on a connection with the peer's port number. Register 0x36 stores the least significant byte and 0x37 stores the most significant byte.
Table 7-41 Their Port Register Bit Definitions (0x36)
Bit Def. Default
Table 7-42
7
6
5
4 0x00
3
2
1
0
Least significant byte of the target port number
Their Port Register Bit Definitions (0x37)
Bit Def. Default
7
6
5
4 0x00
3
2
1
0
Most significant byte of the target port number
7.3.28.
(Read/Write)
Our Port Registers (0x38-0x39)
These registers are used it indicate the source port for an outgoing data packet. When setting a TCP client or sending data using UDP, these registers should be set to the proper value. Normally in client applications, the software increments the value of this register. The TCP and UDP server application should set these registers to be the value used by the server applications. Register 0x38 stores the least significant byte; 0x39 stores the most significant byte.
Table 7-43 Our Port Register Bit Definitions (0x38)
Bit Def. Default
Table 7-44
7
6
5
4 0x00
3
2
1
0
Least significant byte of the local port number
Our Port Register Bit Definitions (0x39)
Bit Def. Default
7
6
5
4 0x00
3
2
1
0
Most significant byte of the local port number
7.3.29.
Socket Status High Register (0x3A)
(Read-Only, Default 0x00)
This register reports the busy status of the socket.
Table 7-45 Socket Status High Register Bit Definitions
Bit Def. Default
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 Snd_Bsy 0
NOTE: Reserved bits are signified by a dash (-). All reserved bits should be written as "0".
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Table 7-46
Socket Status High Register Description
Bit 0
Bit Name Snd_Bsy
Access R
Description This bit indicates that the current socket is busy sending TCP segments. Before the socket is reset, this bit should be 0. 0 = Socket not busy 1 = Socket busy
7.3.30.
Their IP Address Registers (0x3C-0x3F)
(Read/Write, Default 0x00000000)
These registers indicate the destination IP address for the socket. The value must be set prior to activating the socket. The registers can be written in any order.
Table 7-47 Their IP Address Register Bit Definitions (0x3C)
Bit Def. Default
Table 7-48
7
6
5
4 0x00
3
2
1
0
Least significant byte of Destination IP address
Their IP Address Register Bit Definitions (0x3D)
Bit Def. Default
Table 7-49
7
6
5
4 0x00
3
2
1
0
3rd byte of Destination IP address
Their IP Address Register Bit Definitions (0x3E)
Bit Def. Default
Table 7-50
7
6
5
4 0x00
3
2
1
0
2nd byte of Destination IP address
Their IP Address Register Bit Definitions (0x3F)
Bit Def. Default
7
6
5
4 0x00
3
2
1
0
Most significant byte of Destination IP address
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7.3.31.
PPP Control and Status Register (0x60)
(Read/Write, Default 0x00)
This register control the PPP layer and reports its status.
Table 7-51 PPP Control and Status Register Bit Definitions (0x60)
Bit Def. Default
Table 7-52
7 PPP_Int 0
6 Con_Val 0
5 Use_ PAP 0
4 TO_Dis 0
3 PPP_Int_En 0
2 Kick 0
1 PPP_En 0
0 PPP_Up /SRst 0
PPP Control Status Register Description
Bit 7
Bit Name PPP_Int
Access R/W
PPP Interrupt
Description
This bit indicates that the PPP triggered an interrupt condition. Read the PPP interrupt code register to determine the cause. Writing a "1" to this bit position clears the interrupt.
6
Con_Val
R/W
Connection Valid This bit indicates to the network stack that the underlying connection is up and valid. 0 = Connection down 1 = Connection up
5
Use_PAP
R/W
This bit enables PAP authentication within the PPP protocol. If enabled, a PAP request is issued after PAP authentication is negotiated. The PAP string enters through register 0x64. 0 = PAP disabled (default) 1 = PAP enabled
4
TO_Dis
R/W
Timeouts Disabled This bit disables the PPP block from timeouts for diagnostic purposes. It should remain enable for normal operations. 0 = Timeouts enabled (default) 1 = Timeouts disabled
3
PPP_Int_En
R/W
PPP Interrupt Enable This bit enables the PPP interrupt. 0 = PPP Interrupt disabled (default) 1 = PPP Interrupt enabled
2
Kick
W
PPP Kick Start When written to a 1, this bit will start the PPP if it falls into a timeout condition. It clears once the kick operation performs. This bit is self-clearing.
1
PPP_En
R/W
PPP Enable This bit enables the PPP layer. The bit must be set before any transmissions occur. 0 = PPP disabled (default) 1 = PPP enabled
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Bit 0
Bit Name PPP_UP/SRst
Access R/W
Description
When read, this bit indicates when the PPP layer establishes a connection. 0 = PPP Connection down 1 = PPP Connection established When written, this bit will reset the PPP engine. It is selfclearing and goes not need to be written low for normal operations. 0 = PPP Normal operation 1 = PPP Reset
7.3.32.
PPP Interrupt Code (0x61)
(Read-Only, Default 0x00)
This register indicates the interrupt condition that causes the PPP interrupt to trigger.
Table 7-53 PPP Interrupt Code Register Bit Definitions
Bit Def. Default
Table 7-54
7
6
5
4
3
2
1
0
PPP Interrupt Code 0
PPP Interrupt Error Codes
Error Code 0x00 0x01 0x02 0x03 0x04 0x05 Reserved
Definition
PPP Failed initial LCP negotiations PPP Failed NCP negotiations Unexpected LCP closure Termination Request received PAP Failed negotiations
7.3.33.
PPP Max Retry, (0x62)
(Read/Write, Default 0x0A)
This register configures the maximum retry number. This number is used to determine the maximum number of configuration requests that are sent during the PPP negotiation stage.
Table 7-55 PPP Max Retry Register
Bit Def. Default
7
6 0x0
5
4
3
2
1
0
PPP Maximum Retry 0xA
NOTE: Reserved bits are signified by a dash (-).
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7.3.34.
(Write-Only)
PAP String (0x64)
This write-only register enters the string for the PAP configuration request packet. Enter the string according to the format shown Table 7-56.
Table 7-56 PAP String Format
Byte [0] [1] [2] [n] [n+1] [n+2] [n+m+1] Length of username First byte of username Second byte of username
String
Last byte of username (where n is the length of the username string) Length of password First byte of password Last byte of password (where m is the length of the password string)
As an example, if the username string is "joe" and the password is "public", enter the bytes as shown in Table 7-57.
Table 7-57 PAP String Example
byte:0 byte:1 byte:2 byte:3 byte:4 byte:5 byte:6 byte:7 byte:8 byte:9 byte:a
0x03 0x6a 0x6f 0x65 0x06 0x70 0x75 0x62 0x6C 0x69 0x63
Length of username string Character "j" Character "o" Character "e" Length of password string Character "p" Character "u" Character "b" Character "l" Character "I" Character "c"
If PAP is used, the Use_PAP bit must be set in the PPP Control and Status register (0x60) prior to entering the PAP string.
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8.
8.1.
Serial Port Interface
Overview
The S-7600A chip contains a on-board serial port for physical transports. The data format of the serial port is fixed at 1 start bit (logic "0"), 8 data bits, 1 stop bit (logic "1") and no parity bits. The data bits are sent out, least significant bit first. This data format is shown in Figure 8-1. Also included with the serial port is a 16-bit Receive FIFO and an 8-bit Send Buffer.
Figure 8-1 rxd / txd start D0 D1 D2 D3 D4 D5 D6 D7 stop Serial Data Format
8.2.
Serial Port Register Map
Table 8-1 Serial Port Register Map
The following registers are used to communicate with the serial port.
Add 0x08 0x09 0x0A
Register Serial_Port_Config Serial_Port_Int Serial_Port_Int_ Mask S_DAV PT_INT PINT_ EN DCD DSINT DSINT_ EN
Bit Definitions DSR/
HWFC
CTS -
RI -
DTR -
RTS -
SCTL -
-
0x0B 0x0C 0x0D
Serial_Port_Data BAUD_Rate_Div
Serial Port Data Register BAUD Rate Divider Registers
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8.2.1.
Hardware Flow Control (RTS/CTS Handshaking)
The Hardware Flow Control is turned off by default. In this mode, data is transmitted independent of the state of the CTSX signal. While the MPU is in control of the serial port, it can monitor the state of all the serial port control signals and control when data gets sent or received, either through polling the status bits or interrupts. It can also control the RTSX signal by asserting the RTS bit in the Serial Port Config register. When the S-7600A controls the serial port, data will be sent out as soon as it is available from the PPP layer. When receiving data, the software in the MPU control mode should read the data out of the 16-byte FIFO fast enough to prevent buffer overflow. Hardware Flow Control can be turned on by writing a "1" to bit 5 (DSR/HWFC) of the Serial Port Config Register (0x08). With the hardware flow control turned on, full RTS/CTS handshaking is supported. When the serial port detects that CTS is de-asserted, it will stop sending data until CTS is reasserted. Any byte output at the time CTS is de-asserted will complete, but no further bytes will be sent until CTS is asserted. In the other direction, the S-7600A will de-assert RTS if the serial port's 16-byte FIFO is half full. This indicates to the machine on the other end of the serial line to stop transmitting data. The RTS bit will reassert when the MPU or the S-7600A has read data out of the Receive FIFO and room becomes empty. If the machine communicating with the S-7600A over the serial port does not support RTS/CTS handshaking, the Receive FIFO may overflow and data loss will occur.
8.2.2.
Serial Port Control
The control of the serial port is turned over to the MPU by default and after any reset condition. In this mode, any data written to the Serial Port Data register will be sent out and all data received will be made available to the MPU via this same register. Prior to using the data register, the MPU should set the BAUD Rate Div register to the proper setting. An interrupt can be triggered when data is available from the serial port by asserting the PINT_EN bit. When this bit is asserted, an interrupt will trigger any time that there is data available to be read from the port. If there is more then one byte in the Receive FIFO, the interrupt will remain active until all bytes are read. An interrupt can also trigger indicating that the outgoing data byte has been sent, by asserting the DSINT_EN bit. This interrupt will trigger whenever there is no more data to be sent. The MPU turns over control to the S-7600A by asserting the SCTL bit in the Serial Port Config register. When the S-7600A controls the port, the MPU should not access the Serial Port Data register. The S7600A chip will automatically send PPP packets to the serial port and read incoming bytes from the serial port. The serial port interrupts are not valid when the S-7600A controls the port.
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9.
9.1.
Reset Functions
Overview
The S-7600A has two reset functions which are hardware reset and software reset.
9.1.1.
Hardware reset function
The S-7600A operates to be synchronous to the CLK signal(clock input). When the RESETX pin set to low level in one clock period minimum, the S-7600A accept hardware reset input and starts initializing internal circuit at positive edge timing of forth clock. After the RESETX pin return to high level, the S7600A maintains initialized state and turns normal state at positive edge timing of forth clock. See the Figure 9-1.
Min. 1 clock
RESETX
1s
CLK
2n
3r d
4t h
1s
2n d
3r d
4t h normal
initialized
Figure 9-1
Hardware reset timing
9.1.2.
Software reset function
The S-7600A is able to initialize the internal circuit by the General Control Register(0x01). Show the reset timing in case of x80 Family MPU mode. See the Figure 9-2.
CS
RS
WRITEX
Address SD7 to 0
Data h01
BUSYX
CLK
normal state
80 Family MPU mode
Figure 9-2 Software reset timing
initialized state
normal state
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10.
10.1.1.
Application Examples
In case of x80 Family MPU with LCD Controller
x80 Family MPU A0
A1 to A7 IORQ D0 to D7 RD WR RES
S-7600A
RS PSX
Decoder
CS
Driver/ Receiver
SD0 to SD7 READX WRITEX C86
-Personal Computer -MODEM -PDC -PIAFS
LCD Controller (S-4592,etc.)
RS CS D0 to D7 RD WR RESET RES C86 PS
Figure 10-1
Example for x80 Family MPU
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Hardware Specification
10.1.2.
In case of 68k Family MPU with LCD Controller
68k Family MPU A0
A1 to A7 VMA D0 to D7 E R/W RES
S-7600A
RS PSX C86
Decoder
CS
Driver/ Receiver
SD0 to SD7 E (READX) R/WX (WRITEX)
-Personal Computer -MODEM -PDC -PIAFS
LCD Controller (S-4592,etc.)
RS CS D0 to D7 RD WR RESET RES PS C86
Figure 10-2
Example for 68k Family MPU
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S-7600A
Hardware Specification
10.1.3.
In case of Serial interface with LCD Controller
MPU
PORT1 PORT2 PORT3 SOUT SIN SCLK RES RS CS
S-7600A
READX C86
BUSY SI (SD7) SO (SD5) SCL (SD6) PSX
Driver/ Receiver
-Personal Computer -MODEM -PDC -PIAFS
LCD Controller (S-4592,etc.)
RS CS SI SO SCL RESET RES PS C86
Figure 10-3
Example for Serial interface
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Hardware Specification
Seiko Instruments Inc. 1-8, Nakase, Mihama-ku, Chiba-shi, Chiba 261, Japan Components Sales Div. Telephone : +81-43-211-1196 Facsimile : +81-43-211-8032 E-mail : component@sii.co.jp Seiko Instruments USA Inc. Electronic Components Div. 2990 W. Lomita Blvd, Torrance, CA 90505, USA Telephone : +1-909-934-9334 Facsimile : +1-909-975-5699 E-mail : seiko-ecd@salessupport.com http://www.seiko-usa-ecd.com
Notice
If the products, systems, or assemblies, incorporating Seiko Instruments Inc. TCP/IP Network Protocol Stack LSI infringe upon any patent, copyright, or other intellectual property right, Seiko Instruments Inc. shall not be responsible for any matters or damages arising out of or in connection with such patent copyright or other intellectual property right infringement.
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